PFH Calculation of a PID Controller 2oo3 system Implemented in FPGA Using Reliability Block Diagram

Abstract

The Safety control and command system requires a compromise between reliability, availability and security. In this way, the implementation of a system containing a Proportional Integral Derivative Controller (PID) with 2oo3 architecture in FPGA allows the system reliability and reduces the controller conception life cycle. The availability is given by the system redundancy, which is represented by M out of N (MooN), and can tolerate M-N hardware failures to execute the safety function. The system safety is provided by the majority voting arrangement adopted by the active redundancy. To accord credibility to these types of systems, the analysis of a safety related system is an important phase for the classification of the system according to its safety integrity level (SIL). This kind of system can be performed by different methods that are related to international standards such as IEC 61508 [1]. This paper proposes the analysis of a system involving a PID Controller with 2oo3 architecture implemented in FPGA [2] and [3] using a qualitative and a quantitative analysis provided by this standard. The quantitative analysis is performed by the calculation of the system average frequency of dangerous failure (PFH) to define its safety integrity level (SIL). The qualitative analysis is based on the Reliability Block Diagram method [4], [5] and [6].  The results based on IEC 61508 standards will be compared to those obtained by the probabilistic method which uses the system equivalent failure rate in the PFH calculation